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HI-301 thru HI-307
TM
Data Sheet
March 2000
File Number
3125.4
CMOS Analog Switches
The HI-301 thru HI-307 series of switches are monolithic devices fabricated using CMOS technology and the Intersil dielectric isolation process. These switches feature break before-make switching, low and nearly constant ON resistance over the full analog signal range, and low power dissipation, (a few mW for the Hl-301 and HI-303, a few hundred mW for the HI-307). The HI-301 and HI-303 are TTL compatible and have a logic "0" condition with an input less than 0.8V and a logic "1" condition with an input greater than 4V. The HI-307 switches are CMOS compatible and have a low state with an input less than 3.5V and a high state with an input greater than 11V. (See pinouts for switch conditions with a logic "1" input.)
Features
* Analog Signal Range (15V Supplies) . . . . . . . . . . 15V * Low Leakage at 25oC . . . . . . . . . . . . . . . . . . . . . . . 40pA * Low Leakage at 125oC . . . . . . . . . . . . . . . . . . . . . . . 1nA * Low On Resistance at 25oC . . . . . . . . . . . . . . . . . . . 35 * Break-Before-Make Delay . . . . . . . . . . . . . . . . . . . . 60ns * Charge Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . 30pC * TTL, CMOS Compatible * Symmetrical Switch Elements * Low Operating Power (Typ for Hl-301 and HI-303) . . 1.0mW
Ordering Information
PART NUMBER HI9P0301-5 HI1-0303-2 HI1-0303-5 HI9P0303-5 HI9P0303-9 HI1-0307-5 TEMP. RANGE (oC) 0 to 75 -55 to 125 0 to 75 0 to 75 -40 to 85 0 to 75 PACKAGE 14 Ld SOIC 14 Ld CERDIP 14 Ld CERDIP 14 Ld SOIC 14 Ld SOIC 14 Ld CERDIP PKG. NO. M14.15 F14.3 F14.3 M14.15 M14.15 F14.3
Applications
* Sample and Hold (i.e., Low Leakage Switching) * Op Amp Gain Switching (i.e., Low On Resistance) * Portable, Battery Operated Circuits * Low Level Switching Circuits * Dual or Single Supply Systems
Functional Diagram
S IN N P D
Pinouts
Switch States Shown For A Logic "1" Input SPST HI-301 (SOIC) TOP VIEW
NC 1 D1 2 NC 3 S1 4 NC 5 IN 6 GND 7 14 V+ 13 D2 12 NC 11 S2 10 NC 9 NC 8 V-
DUAL SPDT HI-303 (CERDIP, SOIC) HI-307 (CERDIP) TOP VIEW
NC 1 S3 2 D3 3 D1 4 S1 5 IN1 6 GND 7 14 V+ 13 S4 12 D4 11 D2 10 S2 9 IN2 8 V-
LOGIC 0 1
SW1 OFF ON
SW2 ON OFF
LOGIC 0 1
SW1, SW2 OFF ON
SW3, SW4 ON OFF
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000
HI-301 thru HI-307 Schematic Diagrams
SWITCH CELL
A V+ MN1B
MN2B MP5B IN MP4B
MN3B
OUT MN4B MN6B
MP3B
MP2B MP1B V-
A
DIGITAL INPUT BUFFER AND LEVEL SHIFTER
V+ D2A 200 LOGIC IN D1A GND VSWITCH CELL DRIVER (ONE PER SWITCH CELL) MN1A MN2A MN3A MN4A MN5A MN6A MN7A MN8A A A MP1A MP2A MP3A MP4A MP5A MP6A MP7A MP8A
2
HI-301 thru HI-307
Absolute Maximum Ratings
Voltage Between Supplies (V+ to V-) . . . . . . . . . . . . . . . .44V (22V) Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+) +4V to (V-) -4V Analog Input Voltage . . . . . . . . . . . . . . . . . . (V+) +1.5V to (V-) -1.5V Typical Derating Factor . . . . . . . . . 1.5mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 95 40 SOIC Package . . . . . . . . . . . . . . . . . . . 120 N/A Maximum Junction Temperature Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range HI-3XX-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HI-3XX-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC HI-3XX-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Supplies = +15V, -15V; VIN = Logic Input. HI-301 and HI-303: VIN - for Logic "1" = 4V, for Logic "0" = 0.8V. HI-307: VIN - for Logic "1" = 11V, for Logic "0" = 3.5V, Unless Otherwise Specified TEMP (oC) -2 MIN TYP MAX MIN -5, -9 TYP MAX UNITS
PARAMETER DYNAMIC CHARACTERISTICS Switch ON Time, tON (Note 13) Switch OFF Time, tOFF (Note 13) Switch ON Time, tON (Note 14) Switch OFF Time, tOFF (Note 14) Break-Before-Make Delay, tOPEN Charge Injection Voltage, V (Note 7) OFF Isolation (Note 6) Input Switch Capacitance, CS(OFF) Output Switch Capacitance, CD(OFF) Output Switch Capacitance, CD(ON) Digital Input Capacitance, CIN DIGITAL INPUT CHARACTERISTICS Input Low Level, VINL (Note 13) Input High Level, VINH (Note 13) Input Low Level, VINL (Note 14) Input High Level, VINH (Note 14) Input Leakage Current (Low), IINL (Note 5) Input Leakage Current (High), IINH (Note 5) ANALOG SWITCH CHARACTERISTICS Analog Signal Range ON Resistance, rON (Note 2)
25 25 25 25 25 25 25 25 25 25 25
-
210 160 160 100 60 3 60 16 14 35 5
300 250 250 150 -
-
210 160 160 100 60 3 60 16 14 35 5
300 250 250 150 -
ns ns ns ns ns mV dB pF pF pF pF
Full Full Full Full Full Full
4 11 -
-
0.8 3.5 1 1
4 11 -
-
0.8 3.5 1 1
V V V V A A
Full 25 Full
-15 -
35 40 0.04 1
+15 50 75 1 100
-15 -
35 40 0.04 0.2
+15 50 75 5 100
V nA nA
OFF Input Leakage Current, IS(OFF) (Note 3)
25 Full
3
HI-301 thru HI-307
Electrical Specifications
Supplies = +15V, -15V; VIN = Logic Input. HI-301 and HI-303: VIN - for Logic "1" = 4V, for Logic "0" = 0.8V. HI-307: VIN - for Logic "1" = 11V, for Logic "0" = 3.5V, Unless Otherwise Specified (Continued) TEMP (oC) 25 Full ON Leakage Current, ID(ON) (Note 4) 25 Full POWER SUPPLY CHARACTERISTICS Current, I+ (Notes 8, 13) 25 Full Current, I- (Notes 8, 13) 25 Full Current, I+ (Notes 9, 13) 25 Full Current, I- (Notes 9, 13) 25 Full Current, I+ (Notes 10, 14) 25 Full Current, I- (Notes 10, 14) 25 Full Current, I+ (Notes 11, 14) 25 Full Current, I- (Notes 11, 14) 25 Full NOTES: 2. VS = 10V, IOUT = 10mA. On resistance derived from the voltage measured across the switch under these conditions. 3. VS = 14V, VD = 14V. 4. VS = VD = 14V. 5. The digital inputs are diode protected MOS gates and typical leakages of 1nA or less can be expected. 6. VS = 1VRMS , f = 500kHz, CL = 15pF, RL = 1K. 7. VS = 0V, CL = 10nF, Logic Drive = 5V pulse (HI-301 - 303), 15V pulse (HI-307). Switches are symmetrical; S and D may be interchanged. Charge Injection = Q = CL x V. 8. VIN = 4V (one input, all other inputs = 0V). 9. VIN = 0.8V (all inputs). 10. VIN = 15V (all inputs). 11. VIN = 0V (all inputs). 12. To drive from DTL/TTL circuits, pullup resistors to +5V supply are recommended. 13. HI-301 thru HI-303 only. 14. HI-307 only. 0.09 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.5 1 10 100 10 100 10 100 10 100 10 100 10 100 10 100 0.09 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.5 1 100 100 100 100 100 100 100 mA mA A A A A A A A A A A A A A A -2 MIN TYP 0.04 1 0.03 0.5 MAX 1 100 1 100 MIN -5, -9 TYP 0.04 0.2 0.03 0.2 MAX 5 100 5 100 UNITS nA nA nA nA
PARAMETER OFF Output Leakage Current, ID(OFF) (Note 3)
4
HI-301 thru HI-307 Test Circuits and Waveforms
15V S VS = +3V RL 300 LOGIC INPUT GND V-15V V+ D VO CL 33pF SWITCH OUTPUT LOGIC "1" = SWITCH ON LOGIC INPUT 0V VS VINH 50% 50%
90%
10% tOFF
SWITCH TYPE HI-301 and HI-303 HI-307
VINH 4V 15V
0V SWITCH OUTPUT
tON
FIGURE 1A. TEST CIRCUIT FIGURE 1. SWITCH tON AND tOFF
FIGURE 1B. MEASUREMENT POINTS
LOGIC INPUT (V)
+15V V+ RGEN = 0 S D RL 10k CL 10pF
6 4 2 0 LOGIC INPUT HI-301 AND HI-303
VGEN
IN
VVLOGIC GND -15V 0 0.4 0.8 TIME (s) 1.2 1.6
FIGURE 2A. TEST CIRCUIT
FIGURE 2B. TTL LOGIC INPUT
15 HI-307 10 5 0 LOGIC INPUT
OUTPUT VOLTAGE (V)
LOGIC INPUT (V)
10 5 0 VGEN = 10V
(NOTE 16)
0
0.4
0.8 TIME (s)
1.2
1.6
0
0.4
0.8 TIME (s)
1.2
1.6
FIGURE 2C. CMOS LOGIC INPUT
FIGURE 2D. VANALOG = 10V
5
HI-301 thru HI-307 Test Circuits and Waveforms
(Continued)
OUTPUT VOLTAGE (V)
5 0 VGEN = 5V
OUTPUT VOLTAGE (V)
5 0 -5 VGEN = 0V
0
0.4
0.8 TIME (s)
1.2
1.6
0
0.4
0.8 TIME (s)
1.2
1.6
FIGURE 2E. VANALOG = 5V
FIGURE 2F. VANALOG = 0V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
0 -5 VGEN = -5V
0 -5 -10 VGEN = -10V 0 0.4 0.8 TIME (s) 1.2 1.6
0
0.4
0.8 TIME (s)
1.2
1.6
FIGURE 2G. VANALOG = -5V NOTE:
FIGURE 2H. VANALOG = -10V
15. If RGEN , RL or CL is increased, there will be proportional increases in rise and/or fall RC times. FIGURE 2. SWITCHING WAVEFORMS FOR VARIOUS ANALOG INPUT VOLTAGES
15V S1 VS1 = +3V VS2 = +3V S2
V+
D1 D2
OUT 1 OUT 2 LOGIC INPUT 0V LOGIC "1" = SWITCH ON VINH RL1 = RL2 = 300 CL1 = CL2 = 33pF
RL2 LOGIC INPUT GND V-15V
CL2
RL1
CL1
50%
50% OUT 1
SWITCH TYPE HI-301, HI-303 HI-307
VINH 5V 15V
0V SWITCH OUTPUTS 50% 0V tOPEN
OUT 2 50% tOPEN
FIGURE 3A. TEST CIRCUIT
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE DELAY (tOPEN)
6
HI-301 thru HI-307 Typical Performance Curves
80 DRAIN TO SOURCE ON RESISTANCE () DRAIN TO SOURCE ON RESISTANCE () V+ = +15V, V- = -15V 80 TA = 25oC D
60 125oC 25oC -55oC
60
C
40
40
B A
20
20
A B C D
V+ = +15V, V- = -15V V+ = +10V, V- = -10V V+ = +7.5V, V- = -7.5V V+ = +5V, V- = -5V -10 -5 0 5 10 15
0 -15
-10
-5
0
5
10
15
0 -15
DRAIN VOLTAGE (V)
DRAIN VOLTAGE (V)
FIGURE 4. rDS(ON) vs VD
100 V+ = +15V, V- = -15V TA = 25oC, VS = 15V, RL = 2K POWER DISSIPATION (mW) 80 OFF ISOLATION (dB) 10 100
FIGURE 5. rDS(ON) vs VD
V+ = +15V, V- = -15V CLOAD = 30pF, VS = 1VRMS RL = 100 60 RL = 1k 40
HI-301 AND HI-303 1.0
20 HI-307 0.1 1 10 100 1K 10K 100K 1M LOGIC SWITCHING FREQUENCY (50% DUTY CYCLE) (Hz) 0 105
106
107
108
FREQUENCY (Hz)
FIGURE 6. DEVICE POWER DISSIPATION vs SWITCHING FREQUENCY (SINGLE LOGIC INPUT)
10.0 V+ = +15V, V- = -15V 10.0
FIGURE 7. OFF ISOLATION vs FREQUENCY
V+ = +15V, V- = -15V | VD | = | VS | = 14V
SOURCE OR DRAIN OFF LEAKAGE CURRENT (nA)
1.0 ID(ON) (nA) 0.1
1.0
0.1
0.01 25 75 125 TEMPERATURE (oC)
0.01 25
75
125
TEMPERATURE (oC)
FIGURE 8. IS(OFF) OR ID(OFF) vs TEMPERATURE
FIGURE 9. ID(ON) vs TEMPERATURE
The net leakage into the source or drain is the N-Channel leakage minus the P-Channel leakage. This difference can be positive, negative or zero depending on the analog voltage and temperature, and will vary greatly from unit to unit.
7
HI-301 thru HI-307 Typical Performance Curves
60 OUTPUT ON CAPACITANCE (pF)
(Continued)
16
INPUT CAPACITANCE (pF)
50
12
40
8
TRANSITION (INDETERMINATE DUE TO ACTIVE INPUT)
HI-301 AND HI-303
30
4 TRANSITION HI-307
20 0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16 DRAIN VOLTAGE (V) INPUT VOLTAGE (V)
FIGURE 10. OUTPUT ON CAPACITANCE vs DRAIN VOLTAGE
FIGURE 11. DIGITAL INPUT CAPACITANCE vs INPUT VOLTAGE
300 V+ = +15V, V- = -15V VINH = 4.0V, VINL = 0V SWITCHING TIME (ns) SWITCHING TIME (ns) tON 200
300 V+ = +15V, V- = -15V VINH = 15V, VINL = 0V
200 tON
tOFF 100
100 tOFF
-55
-35
-15
5
25
45
65
85
105
125
-55
-35
-15
5
25
45
65
85
105
125
TEMPERATURE (oC)
TEMPERATURE (oC)
FIGURE 12. SWITCHING TIME vs TEMPERATURE, HI-301 AND HI-303
FIGURE 13. SWITCHING TIME vs TEMPERATURE, HI-307
300 300 SWITCHING TIME (ns) V+ = +15V, TA = 25oC VINH = 4V, VINL = 0V SWITCHING TIME (ns) tON V+ = +15V, TA = 25oC VINH = 15V, VINL = 0V
tON
200
200
tOFF
100
tOFF
100
0
5
10
15
0
NEGATIVE SUPPLY (V)
5 10 NEGATIVE SUPPLY (V)
15
FIGURE 14. SWITCHING TIME vs NEGATIVE SUPPLY VOLTAGE, HI-301 AND HI-303
FIGURE 15. SWITCHING TIME vs NEGATIVE SUPPLY VOLTAGE, HI-307
8
HI-301 thru HI-307 Typical Performance Curves
SWITCHING TIME/BREAK-BEFORE-MAKE TIME (s) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 5 10 15 POSITIVE SUPPLY VOLTAGE (V) tOPEN HI-301/303 ONLY tOFF 0.2 0 0 5 10 15 POSITIVE SUPPLY VOLTAGE (V) tON SWITCHING TIME (s)
(Continued)
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 tOFF tON V- = -15V, TA = 25oC VINH = 15V, VINL = 0V
V- = -15V, TA = 25oC VINH = 4.0V, VINL = 0V
FIGURE 16. SWITCHING TIME AND BREAK-BEFORE-MAKE TIME vs POSITIVE SUPPLY VOLTAGE, HI-301 AND HI-303
FIGURE 17. SWITCHING TIME vs POSITIVE SUPPLY VOLTAGE, HI-307
7 INPUT SWITCHING THRESHOLD (V) V- = -15V, TA = 25oC 6 5 4 3 2 HI-301 AND 303 1 0 0 5 10 15 POSITIVE SUPPLY VOLTAGE (V) HI-307
FIGURE 18. INPUT SWITCHING THRESHOLD vs POSITIVE SUPPLY VOLTAGE
9
HI-301 thru HI-307 Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A - B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)
14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.785 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 19.94 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
c1 D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 14 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 14 5.08 1.52 105o 0.38 0.76 0.25 0.038
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
aaa bbb ccc M N
10
HI-301 thru HI-307 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 8.55 3.80 MAX 1.75 0.25 0.51 0.25 8.75 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.3367 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.3444 0.1574
A1 B C D E
A1 0.10(0.004) C
e
B 0.25(0.010) M C AM BS
e H h L N
0.050 BSC 0.2284 0.0099 0.016 14 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 14 0o 6.20 0.50 1.27
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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